FPGA Projects

Real‑time Edge Detection on Basys 3 using an OV7670 Camera and VGA Output

Built a real‑time image processing pipeline in Verilog to capture camera frames from an OV7670, perform edge detection, and display results over VGA on a Basys 3 board using Vivado 2025.2.

4-bit Counter: Circuit Simulator and FPGA Implementation

Simulation of circuit behavior in LTspice and FPGA implementation of a 4-bit counter with J-K flip-flops and a two-stage synchronizer

FPGA Projects at NYCU (2025)

sub-project: FSM-based RCA/CLA with magnitude comparators
sub-project: Simulation of a phase detector

Multiple GMSL Cameras with FPGA (Vecow)

Vivado and Vitis

gPTP Time Sync with FPGA (Vecow)

PetaLinux