4-bit Counter: Circuit Simulator and FPGA Implementation
- This GitHub repo not only analyzes LTspce behavior simulation but also provides testbenches based on both ModelSim and XSim. Besides, the counter design are implemented both in Altera DE2 (video) and Diligent Basys3 (video).
- Designed a 4-bit counter using J-K FFs in LTspice with an R-2R D/A converter and ran simulation.
- Implemented a 4-bit counter in VHDL, synthesized with Quartus, and verified such a design using ModelSim testbenches.
- Developed a two-stage synchronizer to debounce the pushbutton and demonstrated real‑time operation with 7‑segment display on (1) Intel Altera DE2-115 and (2) Diligent Basys 3.
- External Link: GitHub, Report, YouTube
