FPGA Projects at NYCU (2025)
- Project 1: FSM-based RCA/CLA with Magnitude Comparators
- GitHub, Report, YouTube
- Designed and implemented ripple-carry adder (RCA) and carry-lookahead adder (CLA) in VHDL/Verilog and synthesized with Quartus.
- Verified FSM-based designs using ModelSim testbenches covering directed and corner-case stimuli.
- Integrated 8-bit comparators with a 7‑segment display and demonstrated real‑time operation on DE2‑115.
- Project 2: Simulation of Phase Detector (LTspice and ModelSim)
- This report analyzes different types of phase detectors and PLLs and simulates in both LTspice and ModelSim software.
